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Abstract

In this report, we presented an NV Random Access Memory cell using a novel easy and proficient model of Spin Transfer Torque Magnetic Tunnel Junction (STT-MTJ). Magnetic tunnel junction (MTJ) devices are CMOS well suited with high steadiness, high dependability and non-volatility. The combination of magnetic tunnel junction with CMOS circuits in magnetic RAM (MRAM) or Magnetic FPGA can get the digital circuits to major advantages related with non-volatile facility like immediate on/off, Zero standby power use of goods and services. MTJ (Magnetic Tunnel Junction) devices have various advantages over other magneto-resistive devices for use in MRAM cells, like MRAM produces a big signal for the read operation and a varying resistance that can make the circuit. Due to these attributes, MTJ-MRAM can operate at high velocity. A completed simulation model for the 5T and 2MTJ SRAM design is shown in this report, which is grounded on the recently confirmed STT (Spin-Transfer Torque) writing technique which promises to take down the switching current losing to ~150μA and the STT RAM cache reduces total power consumption from 44.6μW -13.2μW. This model has been confirmed in Verilog A language and the whole work carried out and ran out on cadence virtuoso platform at 45nm.

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