Comparative analysis of Dual Tail Comparator using Clock Gating Technique

Authors

Akanksha Singh, ECE Department ITM University , Gwalior (MP)Follow
Ayushi Marwah, Department of Electronics and Communication, ITM University, Gwalior (M.P.)Follow
Shyam Akashe, Head of Department Electronics and Communication ITM University, Gwalior (M.P.)Follow

Abstract

This paper presents the comparison of dynamic latch comparator with dual tail comparator. Dual input in the circuit is compared and single output respective to the input provided is acquired from the opposite end. Comparator circuit should consume less power and should have a high speed of operation. With the proposed design the amenities of the comparator circuit is obtained. Since scaling of transistor size is taking place, so the circuit is designed in 45nm technology. The supply voltage for the circuit is also very low as compared to other conventional based design. With the proposed design the efficiency of the circuit obtained is higher than the conventional design with reduction in the leakage current and leakage power in the design. The circuit is simulated at 45 nm technology with the supply voltage of 0.7 volts.

Recommended Citation

Singh, Akanksha; Marwah, Ayushi; and Akashe, Shyam (2024) "Comparative analysis of Dual Tail Comparator using Clock Gating Technique," American Journal of Electronics & Communication (AJEC): Vol. 1: Iss. 1, Article 8.
Available at: https://research.smartsociety.org/ajec/vol1/iss1/8