Design of 1-bit Full Adder using output wired CMOS Inverter based Threshold Gate

Authors

Mili Sarkar, Electronics and Communication Engineering Institute of Engineering and Management Kolkata, IndiaFollow
G. S. Taki, Electronics and Communication Engineering Institute of Engineering and Management Kolkata, IndiaFollow

Abstract

A new implementation technique of 1-bit Full Adder using output wired CMOS inverter based threshold logic is presented. With the advancement of nano technology threshold gate based logic design has got a new direction. In this paper first carry output is designed using output wired CMOS inverter based majority gate. Then Sum output is designed using Threshold gate. The number of transistor is less than the CMOS based Full Adder Circuit. The major advantage of this CMOS Threshold gate is it’s simplicity. It’s delay time is only around three inverter delays. The proposed design has been verified by means of simulation using PSPICE.

Recommended Citation

Sarkar, Mili and Taki, G. S. (2024) "Design of 1-bit Full Adder using output wired CMOS Inverter based Threshold Gate," American Journal of Electronics & Communication (AJEC): Vol. 1: Iss. 2, Article 5.
Available at: https://research.smartsociety.org/ajec/vol1/iss2/5